Vector machines permit processing of multiple lanes of data in parallel. Throughput of the processor can be increased by increasing the number of lanes. Accordingly, there are oftentimes vector lanes that are inactive due to predication. Inactive vector lanes are also referred to herein as unmasked lanes. Active vector lanes are also referred to herein as masked lanes.
However, with current vector computing processes, a predicated vector instruction is dispatched and issued to all lanes (for a given cycle) regardless of whether the lane is masked or unmasked. Issuing the same vector instructions without consideration as to whether a given lane is active or inactive is inefficient in terms of processing throughput. Namely, utilization of the unmasked lanes in the processing pipeline is essentially foregone.
Therefore, techniques which increase the pipeline utilization and efficiency would be desirable.